1. Field of the Invention
The present invention relates in general to integrated circuit testers and in particular to a driver circuit for producing a phase modulated test signal.
2. Description of Related Art
Recoverable clock receivers are often used in high speed telecommunications systems. A recoverable clock transmission system uses the data transitions within a transmitted data stream to convey timing information rather than sending an additional reference clock signal in parallel with the data signal. The recoverable clock receiver monitors the incoming data stream to "recover" a representative copy of the clock that the transmitter used when transmitting the data stream. Pulses of the recovered clock signal tell the receiver when to sample the data stream.
One problem with a recoverable clock transmission system is that when a data stream has long periods in which state transitions are so few and far between that the receiver is unable to recover the clock signal. Thus the receiver is unable to sample the data stream at the proper times and data reception fails. Many special encoding schemes have been devised to alleviate the problem by trying to insure that state transitions occur frequently. However there are usually some data patterns for which an encoding scheme is unable produce a data signal having sufficiently frequent state changes. Thus while the encoding schemes tend to reduce clock recovery failures, they do not entirely eliminate them.
One measure of a telecommunication receiver's ability to recover a clock signal is its ability to endure "jitter" in a data signal providing a particular data pattern. In telecommunication systems, "jitter" is defined as a periodic time displacement error in state transitions that varies with time in a sinusoidal fashion. Thus in a "jittery" data signal the state transitions do not occur at regular intervals. When the jitter is severe enough, the receiver will not be able to recover the clock signal.
An IC tester can test a recoverable clock receiver by sending it a data signal and sampling the receiver's output to determine if it accurately reflects the data pattern conveyed in the test signal. The receiver's tolerance to jitter can be measured by introducing an appropriate sinusoidal variation in the timing of state changes in the data signal. However, as the speed of recoverable clock communication devices increases it has become more difficult to test receivers for jitter tolerance.
FIG. 1 illustrates a typical "per-pin" integrated circuit tester 10 in block diagram form. Tester 10 includes a separate channel 11 for each pin or terminal of an integrated circuit device under test (DUT) 12. A test is organized into a sequence of test cycles, and during each test cycle each channel 11 can either generate and transmit a test signal to a DUT terminal and/or sample a DUT output signal produced at the DUT terminal to determine its state. Before the start of a test, a host computer 14 transmits a vector data sequence via a bus 16 to each channel 11. Each vector data sequence defines the test activities the channel is to carry out during the test. After storing a vector sequence in each channel, host computer 14 concurrently signals channels 11 to start the test. Each channel 11 then carries out the sequence of test activities defined by its stored vector data sequence. During the test, channels 11 synchronize their activities to a common master clock signal MCLK produced by a clock source 17.
FIG. 2 illustrates a typical tester channel 11 of FIG. 1 in more detailed block diagram form. Referring to FIG. 2, channel 11 includes a vector memory 18 for storing the vector data sequence arriving on bus 16. A START signal sent from host 14 of FIG. 1 via a control line of bus 16 tells a sequencer 20 to begin read addressing vector memory 18. Sequencer 20, clocked by the MCLK signal, sends a new address to vector memory 18 before the start of each test cycle. Thus before the start of each test cycle vector memory 18 reads out vector data indicating the test activity channel 11 is to carry out during a test cycle. The vector data also indicates a time during the test cycle at which the activity is to be carried out. The test vector provides input to a drive circuit 22 and a compare circuit 28.
Drive circuit 22 produces the TEST signal output of channel 11 provided to a terminal of DUT 12 of FIG. 1. The VECTOR data supplied as input to drive circuit 22 at the start of each test cycle may indicate that the TEST signal is to change to a particular state at a particular time during the test cycle. A timing signal generator 24 using the master clock signal MCLK as a timing reference, produces a set of timing signals TS. Each timing signal TS has a period matching that of the test cycle, but the timing signals are evenly distributed in phase so that each timing signal pulse edge marks a different time during a test cycle. Timing signals TS are provided as inputs to drive circuit 22 and compare circuit 28. The VECTOR data indicates the timing of the TEST signal state change by telling drive circuit 22 to select a particular one of the TS signals as a trigger for the state change. The VECTOR data may also tell compare circuit 28 to sample the DUT output signal during the test cycle and to determine whether the sampled test signal state matches an expected state. The VECTOR data indicates the timing of DUT.sub.-- OUT signal sampling by telling compare circuit 28 to select one of the timing signals TS as a trigger for the sampling event.
FIG. 3 illustrates a typical prior art drive circuit 22 of FIG. 2 in block diagram form. Drive circuit 22 includes a decoder 30, a pair of type D flip-flops 32 and 34, an inhibitable driver 36 and a set of multiplexers 38. Driver 36 produces the TEST signal in response to input DRIVE and INHIBIT signals. The INHIBIT signal inhibits the TEST signal when asserted. When the INHIBIT signal is not asserted, the DRIVE signal state controls the TEST signal state. Decoder 30 decodes the VECTOR arriving at the start of each test cycle to produce a pair of indicating signals; a signal D indicating a state to which the DRIVE signal is to be driven and a signal I indicating a state to which the INHIBIT signal is to be driven. The D and I indicating signals drive D inputs of flip-flops 32 and 34, respectively. Decoder 30 also signals multiplexer 38 to select a pair of timing signals TS and to provide them as signals TD and TI to clock inputs of flip-flops 32 and 34, respectively. Flip-flop 32 produces the DRIVE signal at its Q output and flip-flop 34 produces the INHIBIT signal at its Q output.
When, for example, an arriving VECTOR indicates that the INHIBIT signal is to go low at a time T1 and the DRIVE signal is to go high at a time T2 during the next test cycle, decoder 30 immediately drives its output D signal high and its output I signal low. Decoder 30 also signals multiplexers 38 to select a timing signal TS providing a pulse at time T1 as the TI clock input to flip-flop 34 and to select another timing signal TS providing a pulse at time T2 as the TD input to flip-flop 32. Thus at time T1 the TI signal pulse clocks the I signal state onto the Q output of flip-flop 34 thereby pulling down the INHIBIT signal so as to enable driver 36. At time T2 the TD signal pulse clocks the D signal state onto the Q output of flip-flop 32 thereby setting the DRIVE signal high. Driver 36 responds by driving the TEST signal high.
In order to test the jitter tolerance of a recoverable clock receiver using the prior art tester of FIGS. 1-3, one channel's TEST signal output may be used as the signal input to the receiver. The compare circuit of another tester channel can be used to sample the receiver output signal. The vector data input to the channel producing the TEST signal is designed to produce a TEST signal conveying an appropriate data sequence to be supplied to the receiver input. We can introduce jitter into the TEST signal simply by adjusting the edge timing information conveyed in the vector data sequence so that TEST signal state changes vary with time in the desired sinusoidal fashion.
However the ability of drive circuit 22 to resolve signal timing into small increments is limited by the timing resolution provided by timing signals TS produced by timing signal generator 24 of FIG. 2. As DUT operating frequencies increase limitations in timing resolution precludes obtaining the appropriate jitter simply by designing jitter into the test event timing specified by the vector sequence defining the TEST signal behavior. What is needed is a simple and effective system for introducing a specified jitter into a TEST signal output of an integrated circuit tester.